Many multi-channel wire-line communication systems, such as DSL (digital subscribe line) systems and gigabit Ethernet systems suffer from echo and cross channel interferences, i.e., crosstalks. Generally, echo and NEXT cancellers are used to mitigate the effect of echo and NEXT noise. The typical way to implement those noise cancellers is to use finite impulse response (FIR) filters in digital domain. This straightforward approach, however, will lead to a significant hardware complexity if the number of taps in the FIR filters is large. For example, in the typical 10GBase-T application, one echo canceller and three NEXT cancellers are used for each pair of cables. Since there are four pairs of cables (four channels) in 10GBASE-T, a total of four echo cancellers and twelve NEXT cancellers are needed at the receiver end. To achieve high performance noise cancellation, each FIR based echo and NEXT canceller requires hundreds of taps, and then the total number of taps in these cancellers is around 5600˜6800. Furthermore, all these cancellers need to be adapted to accommodate channel variations. Implementing these adaptive cancellers will consume large silicon area and power consumption. Therefore, efficient implementation of these adaptive cancellers is very important for a successful DSP transceiver design.
How to achieve a cost-effective design of adaptive echo and NEXT cancellers in multi-channel DSP transceivers is a challenging task. It is apparent in the industry that the FIR techniques used in 1000Base-T solutions, if implemented in a straightforward way, would result in a complexity increase on the order of 45× over 1000Base-T. By using FFT transformation, approximate complexity saving can be 90%. However, new issues such as block processing latency, increased memory and increased precision, make it unsuitable for the multi-channel wire-line data transmission systems such as 10GBase-T. Because of the inherent time-varying and randomness of the channel impulse responses, simple techniques to extend the length of the impulse response to be cancelled, such as continuous-time analog filters or infinite impulse response (IIR) digital filters are not acceptable as flexible solutions. The problem becomes even worse when introducing Tomlinson-Harashima precoding (TH precoding) in 10GBase-T as the inputs to echo and NEXT cancellers are no longer simple PAM-M symbols but numbers uniformly distributed on [−M, M). These make look-ahead and pre-computation techniques difficult to apply (See, e.g., K. K. Parhi, “Pipelining of Parallel Multiplexer Loops and Decision Feedback Equalizers,” in Proceedings of ICASSP 2004, vol. 5, pp. 21-24, May 2004). Furthermore, the word-length of these inputs needs to be long enough (i.e., 10-bit) to achieve required noise cancellation level. Thus, the implementation cost of these adaptive echo and NEXT cancellers increases significantly.
To solve these problems, a new word-length reduction scheme was proposed in one of previous inventions (See, Keshab K. Parhi, and Yongru Gu, “System and method for low-power echo and NEXT cancellers”, U.S. patent application Ser. No. 11/487,041, filed on Jul. 13, 2006), where the hardware cost of these echo and NEXT cancellers was reduced by about 10.82% without any performance loss. However, the proposed word-length reduction technique can not be easily applied to the weight (coefficient) adaptation part in the adaptive filters. Complexity analysis also showed that the hardware cost saving was mainly due to hardware cost reduction of the filter part in these adaptive cancellers. Therefore, the problem of reducing hardware cost of the weight update part in these adaptive cancellers remained unsolved.
What is needed is a new design methodology and an implementation method to deal with the weight update part in these adaptive echo and NEXT cancellers so that the overall hardware cost of implementing these cancellers can be further reduced.